1. Field of the Invention
The present invention relates to a nonvolatile memory device with simultaneous read/write.
2. Description of the Related Art
To optimize read/write performance of nonvolatile memory devices, it is extremely important to be able to execute parallel read/write operations on more than one cell. Various solutions are known to the art which enable increase of the number of memory cells that are selected simultaneously to be read or written (page read/write or “burst mode”). The same type of operation, either read or write, is usually performed on all of the cells selected.
During reading, in practice, the selected cells are connected to respective sense amplifiers, which compare the threshold voltages of the cells with the threshold voltages of respective reference cells.
During writing, which may envisage programming or erasing of the selected cells, a cycle comprising two steps is executed at least once. Initially, the selected cells are biased with preset voltages and/or biasing currents so as to modify their threshold voltages. Then, reading is performed to verify the value actually reached by the threshold voltages. If this value is insufficient, the cycle is repeated. Moreover, in the case of multilevel memories, it is in any case necessary to execute more than one cycle.
Writing cannot in general be performed simultaneously with reading. In fact, during verifying of the threshold voltages, the cells must be connected to the sense amplifiers, which thus are not available for reading other cells. In addition, verifying is performed synchronously with an internal timing signal of the memory devices, while ordinary reading is asynchronous. It is consequently evident that also the driving signals and reference signals are different for verifying and reading.
To overcome the described drawbacks, architectures of nonvolatile memories have been proposed which enable simultaneous reading on a first set of cells and writing on a second set of cells (dual working). According to these solutions, in practice, the memory array is divided into sections, and associated to each section is a set or bank of sense amplifiers and a column decoder circuit. The banks of sense amplifiers are independent of one another and thus may be driven simultaneously in different ways. More precisely, while a first bank of sense amplifiers is driven in a synchronous way (verify), a second bank may be driven in an asynchronous way (read). In this way, it is therefore possible to perform simultaneously read and write operations, provided that cells are selected belonging to distinct sections of the memory.
Also this solution presents evident limits in so far as the memory array cannot be divided into a large number of sections. In fact, since each section should be associated to a respective bank of sense amplifiers, fractioning of the memory also entails an increase in the overall dimensions of the device; the more the memory is fractioned, the greater the overall dimensions. Consequently, the memory arrays normally comprise two or at the most four sections. On the other hand, the low fractioning of the memory causes simultaneous access to reading and writing to be relatively infrequent and thus far from effective. In any case, in fact, it is not possible to simultaneously read and write cells belonging to the same section.